The present invention relates to a method of manufacturing a semiconductor device having sub-micron features. The present invention has particular applicability in manufacturing semiconductor devices with a design rule of about 0.18 microns and under with accurately dimensioned conductive features.
The escalating requirements for high density and performance associated with ultra-large scale integration require responsive changes in electrical interconnected patterns, which is considered one of the most demanding aspects of ultra-large scale integration technology. High-density demands for ultra-large scale integration semiconductor wiring require increasingly denser arrays with minimal spacing between conductive lines. This problem is exacerbated in manufacturing semiconductor devices having a design rule of about 0.18 microns and under.
In general, semiconductor devices comprise a substrate and elements such as transistors and/or memory cells thereon. Various interconnection layers are formed on the semiconductor substrate to electrically connect these elements to each other and to external circuits. The formation of interconnection layers is partly accomplished by employing conventional photolithographic techniques to form a photoresist mask comprising a pattern and transferring the pattern to an underlying layer or composite by etching the exposed underlying regions.
In accordance with conventional practices, interconnect structures comprise electrically conductive layers such as aluminum or alloys thereof. In the process of patterning the interconnect structure, an anti-reflective coating (ARC) is typically provided between the photoresist and the conductive layer to avoid deleterious reflections from the underlying conductive layer during patterning of the photoresist. The ARC can reduce the reflectivity of, for example, an aluminum metal layer to 25-30% from a reflectivity of about 80-90%. ARCs conventionally comprise materials such as silicon nitride, silicon oxynitride and titanium nitride, and are chosen for their optical properties and compatibility with the underlying conductive layer. However, many of the desirable ARCs contain basic components, such as nitrogen, which adversely interact with the photoresist material thereon during the photolithographic process.
A conventional interconnect structure is shown in FIG. 1, wherein substrate 8 has dielectric layer 10 thereon, conductive layer 12 on dielectric layer 10, ARC 14 on conductive layer 12 and a photoresist coating 16 on ARC 14. In very large scale integrated circuit applications, dielectric 10 has several thousand openings which can be either vias or lateral metallization lines where the metallization pattern serves to interconnect structures on or in the semiconductor substrate Dielectric layer 10 can comprise inorganic layers such as silicon dioxide, silicon nitride, silicon oxynitride, etc. or organic layers such as polyimide or combinations of both. Conductive layer 12 typically comprises a metal layer such as aluminum, copper, titanium, binary alloys thereof, ternary alloys, such as Alxe2x80x94Pdxe2x80x94Cu, Alxe2x80x94Pdxe2x80x94Nb, Alxe2x80x94Cuxe2x80x94Si or other similar low resistivity metal or metal based alloys, ARC 14 typically comprises a nitride of silicon or a nitride of a metal such as titanium.
To achieve high density line wiring, photoresist coating 16 is typically a deep ultraviolet (DUV) radiation sensitive photoresist capable of achieving line width resolutions of about 0.30 microns. During the photolithographic process, radiation is passed through mask 18 defining a desired conductive pattern to imagewise expose photoresist coating 16. After exposure to radiation, the photoresist layer is developed to form a relief pattern therein. It has been observed, however, that a residue remains at the photoresist interface and ARC, near the developed photoresist sidewall, resulting in a parabolic appearance, 22a and 22b, at the base of the photoresist known as xe2x80x9cfootingxe2x80x9d.
A conventional interconnect architecture after patterning of the photoresist is shown in FIG. 2. As shown, dielectric layer 10 overlays a device or a region of the semiconductor (not shown), conductive layer 12 overlays dielectric layer 10, ARC 14 overlays conductive layer 12 and a patterned photoresist, represented by photoresist line 20 overlays on ARC 14.
Photoresist line 20 of FIG. 2 further illustrates the footing phenomena where it shown that a portion of the base of the photoresist remains after patterning. The footing problem is typical of conventional photolithographic techniques employing a photoresist coating over an ARC in the manufacture of interconnections. Footing of the photoresist during patterning results in a loss of dimensional control in the subsequently patterned underlying conductive layer limiting the ability to resolve small spaces between conductive lines and thus limiting the wiring density.
Accordingly, there exists a need for a method of manufacturing a semiconductor device wherein a photoresist overlying an ARC can be accurately patterned. There is also a need for improving line width accuracy to achieve fine line conductive patterns with minimal inter-wiring spaces.
An advantage of the present invention is a semiconductor device having accurately dimensioned conductive features.
Another advantage of the present invention is a process of depositing an oxide film on a substrate.
A further advantage of the present invention is a process of manufacturing a semiconductor device by depositing an oxide film substantially free of nitrogen or other components that can adversely interact with a photoresist coating thereon.
Additional advantages and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the invention. The advantages of the invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a semiconductor device comprising: a conductive layer; an anti-reflective coating on the conductive layer; and an oxide film on the anti-reflective coating. It is advantageous for the oxide film to have a thickness no greater than about 350 xc3x85 and to be free or substantially free of components that can adversely interact with a photoresist coating. The oxide film should be substantially free of components that act as bases, such as nitrogen components, which can poison the photoresist material during patterning of the photoresist.
Another aspect of the present invention is a method of depositing silicon oxide on a substrate. The method comprises: placing the substrate in a deposition chamber; evacuating the deposition chamber; introducing an organosilicon compound in the deposition chamber; introducing an oxidizing gas in the deposition chamber for reacting with the organosilicon compound; and reacting the organosilicon compound with the oxidizing gas to deposit silicon oxide on the substrate. It is advantageous to deposit the silicon oxide as a thin film having a thickness no greater than about 350 xc3x85, e.g., no greater than 300 xc3x85.
A further aspect of the present invention is a method of manufacturing a semiconductor device. The method comprises: forming a layer of a conductive material; forming an anti-reflective coating on the conductive layer; depositing an oxide film on the anti-reflective coating substantially free of basic components; forming a layer of photoresist material on the oxide film; and patterning the photoresist to form a photoresist mask.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the present invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawing and description are to be regarded as illustrative in nature, and not as restrictive.